1. Field
Various features relate to a crack stopping structure in wafer level packaging (WLP).
2. Background
A typical die is manufactured by depositing several metal layers and several dielectric layers on top of a substrate. The die is manufactured by using a wafer level packaging (WLP) process. The substrate, metal layers and dielectric layers are what form the circuit elements of the die. Multiple dies are usually manufactured on a wafer. FIG. 1 illustrates a plan view of a wafer 100 that includes several uncut dies 102. Each uncut die includes a substrate, metal layers and dielectric layers. The wafer 100 is then cut into individual/single dies. FIG. 1 also illustrates vertical and horizontal scribe lines 102-104. Scribe lines are portions of the wafer 100 that are cut in order to manufacture the individual dies (e.g., die 102).
FIG. 2 illustrates a side view of a wafer. Specifically, FIG. 2 illustrates a side view of a portion of a wafer 200. The wafer 200 includes several metal and dielectric layers 202, a pad 204, a passivation layer 206, a first insulation layer 208, a first metal layer 210, a second insulation layer 212, and an under bump metallization (UBM) layer 214. FIG. 2 also illustrates a solder ball 216 on the wafer 200. Specifically, the solder ball 216 is coupled to the UBM layer 214. The pad 204, the first metal layer 210 and the UBM layer 214 are a conductive material (e.g., copper). The first insulation layer 208 and the second insulation layer 212 are polyimide layers (PI), Polybenzoxazole (PBO) or other polymer layers used for repassivation. FIG. 2 also illustrates a region of the wafer 200 that will be cut to create individual dies. This region of the wafer 200 is illustrated by the scribe line 218, which may correspond to either of the scribe lines 104-106 of FIG. 1.
During the process of cutting the wafer (e.g., wafers 100, 200) into one or more dies, a lot of stress (e.g., thermal stress, mechanical stress) is applied to the die. The resulting stress on the die may affects components of the die and/or the package, including the metal layers, the dielectric layers, the passivation layer, the UBM layer, and/or the solder balls.
In addition, a die and/or wafer level package (WLP) may be subject to stress (e.g., thermal stress, mechanical stress) during (1) the process of attaching the die and/or WLP to a printed circuit board (PCB), (2) a temperature reliability test, (3) the field life span of the die, and/or (4) during drop/shock/bending events. For example, during a chip/die attach process to a PCB (where the temperature goes from ˜25 C. to ˜230 C. then to ˜25 C. again in some instances), different components will expand and shrink at different rates because different components have different coefficient of thermal expansion (CTE). For instance, the die and/or WLP (which is made of silicon) has a CTE of about 2.7 ppm, while the PCB has a CTE that is greater than 10 ppm (mostly about 17 ppm). Moreover, the die and/or WLP is coupled to the PCB by solder bump or Copper bump interconnects. The stress on the die (or WLP) comes from the difference in CTEs (CTE mismatch) between the die and the PCB and how they are coupled to each other. Furthermore, after the die and/or WLP is mounted onto the PCB, it will experience temperature swings as part of field conditions. This will cause stress on the dies as well. Moreover, during package development, there are specific board level reliability tests that a WLP must pass. For example, a WLP needs to pass a temperature cycling reliability test and a drop test. In device field condition, there will be drop or shock or bending events that will generate stress in dies. In all these scenarios, die corner areas will usually have the highest stress thus cracks may be generated from die corners first.
Therefore, there is a need for a design to stop and/or prevent the propagation of a crack and/or chipping of a die.